[kaffe] mipsel JIT3
stack at cs.utah.edu
Sat Mar 6 15:01:02 PST 2004
On Mar 5, 2004, at 4:24 PM, Casey Marshall wrote:
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>>>>>> "Kevin" == Kevin D Kissell <kevink at mips.com> writes:
>>> * If I renumber the float registers from 32 to 63, the spill
>>> problem doesn't happen, but I get a bus error when the `call'
>>> instruction is reached. This happens because the constant pool code
>>> tries to restore register gp from fp, and it looks like fp gets
>>> clobbered before this can happen.
> Kevin> The code generation in jit3-mips.def is going to generate all
> Kevin> sorts of broken code if you allow those values to go above 31,
> Kevin> I think. There is no masking of the shifted values as the
> Kevin> instruction words are being created.
> I masked all the registers when generating instructions, and with the
> float registers renumbered all of the test/internal tests pass.
> Kaffe itself won't yet load, however.
Well, its progress...
> This solution is obviously a hack;
I don't think so, it should always be pretty easy for the backend to
map the regno value to whatever needs to be put in the instruction.
> the correct fix is probobly to fix
> register.c to not assume that regno is an index into reginfo.
I'm hesitant to mess with the register allocator too much, especially
since it might break the other backends...
> Unrelated question to the peanut gallery: currently the stack trace I
> get when Kaffe is loading (an "Internal error: caught an unexpected
> exception.") goes all the way back to
> java.lang.VMThrowable.fillInStackTrace(VMThrowable.java:native). Is
> this just a symptom of an exception being thrown early, or is this yet
> another problem with the MIPS backend?
Most likely its normal, send the whole print out if you're really
> Casey Marshall || rsdio at metastatic.org
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