[kaffe] CVS kaffe (dalibor): Fixed compilation problems on m68k-netbsd with jit3
Kaffe CVS
cvs-commits at kaffe.org
Mon May 31 10:24:02 PDT 2004
PatchSet 4798
Date: 2004/05/31 17:15:08
Author: dalibor
Branch: HEAD
Tag: (none)
Log:
Fixed compilation problems on m68k-netbsd with jit3
2004-05-31 Dalibor Topic <robilad at kaffe.org>
* config/m68k/jit3-m68k.def:
fixed WOUT and LOUT calls to use jit3 syntax.
Reported by: Riccardo Mottola <zuse at libero.it>
Members:
ChangeLog:1.2367->1.2368
config/m68k/jit3-m68k.def:1.6->1.7
Index: kaffe/ChangeLog
diff -u kaffe/ChangeLog:1.2367 kaffe/ChangeLog:1.2368
--- kaffe/ChangeLog:1.2367 Sun May 30 20:37:06 2004
+++ kaffe/ChangeLog Mon May 31 17:15:08 2004
@@ -1,3 +1,10 @@
+2004-05-31 Dalibor Topic <robilad at kaffe.org>
+
+ * config/m68k/jit3-m68k.def:
+ fixed WOUT and LOUT calls to use jit3 syntax.
+
+ Reported by: Riccardo Mottola <zuse at libero.it>
+
2004-05-30 Guilhem Lavaux <guilhem at kaffe.org>
* config/powerpc/darwin/md.h: Added a few includes.
Index: kaffe/config/m68k/jit3-m68k.def
diff -u kaffe/config/m68k/jit3-m68k.def:1.6 kaffe/config/m68k/jit3-m68k.def:1.7
--- kaffe/config/m68k/jit3-m68k.def:1.6 Tue Feb 10 17:22:00 2004
+++ kaffe/config/m68k/jit3-m68k.def Mon May 31 17:15:10 2004
@@ -92,8 +92,8 @@
{
debug(("addl #%d, %s\n", imm, regname(dst)));
assert_dreg(dst);
- WOUT = 0xD080 | (dst << 9) | MODE_src_imm;
- LOUT = imm;
+ WOUT(0xD080 | (dst << 9) | MODE_src_imm);
+ LOUT(imm);
}
static inline void
@@ -102,7 +102,7 @@
debug(("addl %s, %s\n", regname(src), regname(dst)));
assert_dreg(src);
assert_dreg(dst);
- WOUT = 0xD080 | (dst << 9) | (MODE_d << 3) | (src & 7);
+ WOUT(0xD080 | (dst << 9) | (MODE_d << 3) | (src & 7));
}
#if !defined(HAVE_NO_ADDAW)
@@ -112,8 +112,8 @@
debug(("addaw #%d, %s\n", imm, regname(dst)));
assert_s16(imm);
assert_areg(dst);
- WOUT = 0xD0C0 | ((dst & 7) << 9) | MODE_src_imm;
- WOUT = imm;
+ WOUT(0xD0C0 | ((dst & 7) << 9) | MODE_src_imm);
+ WOUT(imm);
}
#endif
@@ -122,8 +122,8 @@
{
debug(("addal #%d, %s\n", imm, regname(dst)));
assert_areg(dst);
- WOUT = 0xD1C0 | ((dst & 7) << 9) | MODE_src_imm;
- LOUT = imm;
+ WOUT(0xD1C0 | ((dst & 7) << 9) | MODE_src_imm);
+ LOUT(imm);
}
static inline void
@@ -132,7 +132,7 @@
debug(("addal %s, %s\n", regname(src), regname(dst)));
assert_dreg(src);
assert_areg(dst);
- WOUT = 0xD1C0 | ((dst & 7) << 9) | (MODE_d << 3) | (src & 7);
+ WOUT(0xD1C0 | ((dst & 7) << 9) | (MODE_d << 3) | (src & 7));
}
static inline void
@@ -141,7 +141,7 @@
debug(("addql #%d, %s\n", imm, regname(dst)));
assert(imm >= 1 && imm <= 8);
assert_areg(dst);
- WOUT = 0x5080 | ((imm & 7) << 9) | (MODE_a << 3) | (dst & 7);
+ WOUT(0x5080 | ((imm & 7) << 9) | (MODE_a << 3) | (dst & 7));
}
static inline void
@@ -150,7 +150,7 @@
debug(("addql #%d, %s\n", imm, regname(dst)));
assert(imm >= 1 && imm <= 8);
assert_dreg(dst);
- WOUT = 0x5080 | ((imm & 7) << 9) | (MODE_d << 3) | (dst & 7);
+ WOUT(0x5080 | ((imm & 7) << 9) | (MODE_d << 3) | (dst & 7));
}
static inline void
@@ -159,7 +159,7 @@
debug(("addxl %s, %s\n", regname(src), regname(dst)));
assert_dreg(src);
assert_dreg(dst);
- WOUT = 0xD180 | (dst << 9) | src;
+ WOUT(0xD180 | (dst << 9) | src);
}
static inline void
@@ -167,8 +167,8 @@
{
debug(("andl #0x%x, %s\n", imm, regname(dst)));
assert_dreg(dst);
- WOUT = 0xC080 | (dst << 9) | MODE_src_imm;
- LOUT = imm;
+ WOUT(0xC080 | (dst << 9) | MODE_src_imm);
+ LOUT(imm);
}
static inline void
@@ -177,7 +177,7 @@
debug(("andl %s, %s\n", regname(src), regname(dst)));
assert_dreg(src);
assert_dreg(dst);
- WOUT = 0xC080 | (dst << 9) | (MODE_d << 3) | (src & 7);
+ WOUT(0xC080 | (dst << 9) | (MODE_d << 3) | (src & 7));
}
static inline void
@@ -186,7 +186,7 @@
debug(("asr #%d, %s\n", imm, regname(dst)));
assert_dreg(dst);
assert(imm >= 1 && imm <= 8);
- WOUT = 0xE080 | ((imm & 7) << 9) | dst;
+ WOUT(0xE080 | ((imm & 7) << 9) | dst);
}
static inline void
@@ -195,15 +195,15 @@
debug(("asr %s, %s\n", regname(src), regname(dst)));
assert_dreg(src);
assert_dreg(dst);
- WOUT = 0xE0A0 | ((src & 7) << 9) | dst;
+ WOUT(0xE0A0 | ((src & 7) << 9) | dst);
}
static inline void
op_blo_16(int disp)
{
debug(("blo %+d\n", disp));
- WOUT = 0x6500;
- WOUT = disp;
+ WOUT(0x6500);
+ WOUT(disp);
}
#if defined(HAVE_NO_LONG_BRANCHES)
@@ -212,56 +212,56 @@
op_beq_16(int disp)
{
debug(("beq %+d\n", disp));
- WOUT = 0x6700;
- WOUT = disp;
+ WOUT(0x6700);
+ WOUT(disp);
}
static inline void
op_bne_16(int disp)
{
debug(("bne %+d\n", disp));
- WOUT = 0x6600;
- WOUT = disp;
+ WOUT(0x6600);
+ WOUT(disp);
}
static inline void
op_blt_16(int disp)
{
debug(("blt %+d\n", disp));
- WOUT = 0x6D00;
- WOUT = disp;
+ WOUT(0x6D00);
+ WOUT(disp);
}
static inline void
op_ble_16(int disp)
{
debug(("ble %+d\n", disp));
- WOUT = 0x6F00;
- WOUT = disp;
+ WOUT(0x6F00);
+ WOUT(disp);
}
static inline void
op_bgt_16(int disp)
{
debug(("bgt %+d\n", disp));
- WOUT = 0x6E00;
- WOUT = disp;
+ WOUT(0x6E00);
+ WOUT(disp);
}
static inline void
op_bge_16(int disp)
{
debug(("bge %+d\n", disp));
- WOUT = 0x6C00;
- WOUT = disp;
+ WOUT(0x6C00);
+ WOUT(disp);
}
static inline void
op_bra_16(int disp)
{
debug(("bra %+d\n", disp));
- WOUT = 0x6000;
- WOUT = disp;
+ WOUT(0x6000);
+ WOUT(disp);
}
#else
@@ -270,64 +270,64 @@
op_beq_32(int disp)
{
debug(("beq %+d\n", disp));
- WOUT = 0x67FF;
- LOUT = disp;
+ WOUT(0x67FF);
+ LOUT(disp);
}
static inline void
op_bne_32(int disp)
{
debug(("bne %+d\n", disp));
- WOUT = 0x66FF;
- LOUT = disp;
+ WOUT(0x66FF);
+ LOUT(disp);
}
static inline void
op_blt_32(int disp)
{
debug(("blt %+d\n", disp));
- WOUT = 0x6DFF;
- LOUT = disp;
+ WOUT(0x6DFF);
+ LOUT(disp);
}
static inline void
op_ble_32(int disp)
{
debug(("ble %+d\n", disp));
- WOUT = 0x6FFF;
- LOUT = disp;
+ WOUT(0x6FFF);
+ LOUT(disp);
}
static inline void
op_bgt_32(int disp)
{
debug(("bgt %+d\n", disp));
- WOUT = 0x6EFF;
- LOUT = disp;
+ WOUT(0x6EFF);
+ LOUT(disp);
}
static inline void
op_bge_32(int disp)
{
debug(("bge %+d\n", disp));
- WOUT = 0x6CFF;
- LOUT = disp;
+ WOUT(0x6CFF);
+ LOUT(disp);
}
static inline void
op_blo_32(int disp)
{
debug(("blo %+d\n", disp));
- WOUT = 0x65FF;
- LOUT = disp;
+ WOUT(0x65FF);
+ LOUT(disp);
}
static inline void
op_bra_32(int disp)
{
debug(("bra %+d\n", disp));
- WOUT = 0x60FF;
- LOUT = disp;
+ WOUT(0x60FF);
+ LOUT(disp);
}
#endif
@@ -335,8 +335,8 @@
op_jsr_32(int disp)
{
debug(("jsr %+d\n", disp));
- WOUT = 0x4EB9;
- LOUT = disp;
+ WOUT(0x4EB9);
+ LOUT(disp);
}
static inline void
@@ -344,7 +344,7 @@
{
debug(("clrl %s\n", regname(dst)));
assert_dreg(dst);
- WOUT = 0x4280 | (MODE_d << 3) | (dst & 7);
+ WOUT(0x4280 | (MODE_d << 3) | (dst & 7));
}
static inline void
@@ -353,7 +353,7 @@
debug(("cmpl %s, %s\n", regname(src1), regname(src2)));
assert_dreg(src1);
assert_dreg(src2);
- WOUT = 0xB080 | (src2 << 9) | (MODE_d << 7) | (src1 & 7);
+ WOUT(0xB080 | (src2 << 9) | (MODE_d << 7) | (src1 & 7));
}
static inline void
@@ -362,7 +362,7 @@
debug(("cmpl %s, %s\n", regname(src1), regname(src2)));
assert_areg(src1);
assert_areg(src2);
- WOUT = 0xB1C0 | (src2 << 9) | (MODE_a << 3) | (src1 & 7);
+ WOUT(0xB1C0 | (src2 << 9) | (MODE_a << 3) | (src1 & 7));
}
static inline void
@@ -370,8 +370,8 @@
{
debug(("cmpil #%d, %s\n", imm, regname(src2)));
assert_areg(src2);
- WOUT = 0x0C80 | (MODE_a << 3) | (src2 & 7);
- LOUT = imm;
+ WOUT(0x0C80 | (MODE_a << 3) | (src2 & 7));
+ LOUT(imm);
}
static inline void
@@ -379,8 +379,8 @@
{
debug(("cmpil #%d, %s\n", imm, regname(src2)));
assert_dreg(src2);
- WOUT = 0x0C80 | (MODE_d << 3) | (src2 & 7);
- LOUT = imm;
+ WOUT(0x0C80 | (MODE_d << 3) | (src2 & 7));
+ LOUT(imm);
}
static inline void
@@ -390,8 +390,8 @@
assert_dreg(src);
assert_dreg(r);
assert_dreg(q);
- WOUT = 0x4C40 | (MODE_d << 3) | (src & 7);
- WOUT = 0x0800 | (q << 12) | r;
+ WOUT(0x4C40 | (MODE_d << 3) | (src & 7));
+ WOUT(0x0800 | (q << 12) | r);
}
static inline void
@@ -400,7 +400,7 @@
debug(("eorl %s, %s\n", regname(src), regname(dst)));
assert_dreg(src);
assert_dreg(dst);
- WOUT = 0xB180 | ((src & 7) << 9) | (MODE_d << 3) | (dst & 7);
+ WOUT(0xB180 | ((src & 7) << 9) | (MODE_d << 3) | (dst & 7));
}
static inline void
@@ -408,7 +408,7 @@
{
debug(("extbl %s\n", regname(dst)));
assert_dreg(dst);
- WOUT = 0x49C0 | dst;
+ WOUT(0x49C0 | dst);
}
static inline void
@@ -416,7 +416,7 @@
{
debug(("extwl %s\n", regname(dst)));
assert_dreg(dst);
- WOUT = 0x48C0 | dst;
+ WOUT(0x48C0 | dst);
}
#if !defined(HAVE_NO_EXG)
@@ -426,7 +426,7 @@
debug(("exg %s, %s\n", regname(r1), regname(r2)));
assert_areg(r1);
assert_areg(r2);
- WOUT = 0xC148 | ((r1 & 7) << 9) | (r2 & 7);
+ WOUT(0xC148 | ((r1 & 7) << 9) | (r2 & 7));
}
static inline void
@@ -435,7 +435,7 @@
debug(("exg %s, %s\n", regname(r1), regname(r2)));
assert_dreg(r1);
assert_areg(r2);
- WOUT = 0xC188 | (r1 << 9) | (r2 & 7);
+ WOUT(0xC188 | (r1 << 9) | (r2 & 7));
}
static inline void
@@ -444,7 +444,7 @@
debug(("exg %s, %s\n", regname(r1), regname(r2)));
assert_dreg(r1);
assert_dreg(r2);
- WOUT = 0xC140 | (r1 << 9) | r2;
+ WOUT(0xC140 | (r1 << 9) | r2);
}
#endif
@@ -453,7 +453,7 @@
{
debug(("jmp (%s)\n", regname(dst)));
assert_areg(dst);
- WOUT = 0x4EC0 | (MODE_ind << 3) | (dst & 7);
+ WOUT(0x4EC0 | (MODE_ind << 3) | (dst & 7));
}
static inline void
@@ -461,7 +461,7 @@
{
debug(("jsr (%s)\n", regname(dst)));
assert_areg(dst);
- WOUT = 0x4E80 | (MODE_ind << 3) | (dst & 7);
+ WOUT(0x4E80 | (MODE_ind << 3) | (dst & 7));
}
static inline void
@@ -470,8 +470,8 @@
debug(("linkw %s, #%d\n", regname(areg), disp));
assert_s16(disp);
assert_areg(areg);
- WOUT = 0x4E50 | (areg & 7);
- WOUT = disp;
+ WOUT(0x4E50 | (areg & 7));
+ WOUT(disp);
}
static inline void
@@ -480,7 +480,7 @@
debug(("lsl #%d, %s\n", imm, regname(dst)));
assert_dreg(dst);
assert(imm >= 1 && imm <= 8);
- WOUT = 0xE188 | ((imm & 7) << 9) | dst;
+ WOUT(0xE188 | ((imm & 7) << 9) | dst);
}
static inline void
@@ -489,7 +489,7 @@
debug(("lsl %s, %s\n", regname(src), regname(dst)));
assert_dreg(src);
assert_dreg(dst);
- WOUT = 0xE1A8 | ((src & 7) << 9) | dst;
+ WOUT(0xE1A8 | ((src & 7) << 9) | dst);
}
static inline void
@@ -498,7 +498,7 @@
debug(("lsr #%d, %s\n", imm, regname(dst)));
assert_dreg(dst);
assert(imm >= 1 && imm <= 8);
- WOUT = 0xE088 | ((imm & 7) << 9) | dst;
+ WOUT(0xE088 | ((imm & 7) << 9) | dst);
}
static inline void
@@ -507,7 +507,7 @@
debug(("lsr %s, %s\n", regname(src), regname(dst)));
assert_dreg(src);
assert_dreg(dst);
- WOUT = 0xE0A8 | ((src & 7) << 9) | dst;
+ WOUT(0xE0A8 | ((src & 7) << 9) | dst);
}
static inline void
@@ -516,8 +516,7 @@
debug(("moveb (%s), %s\n", regname(src), regname(dst)));
assert_areg(src);
assert_dreg(dst);
- WOUT = (0x1000 | ((dst & 7) << 9) | (MODE_d << 6)
- | (MODE_ind << 3) | (src & 7));
+ WOUT(0x1000 | ((dst & 7) << 9) | (MODE_d << 6) | (MODE_ind << 3) | (src & 7));
}
static inline void
@@ -526,8 +525,7 @@
debug(("moveb %s, (%s)\n", regname(src), regname(dst)));
assert_dreg(src);
assert_areg(dst);
- WOUT = (0x1000 | ((dst & 7) << 9) | (MODE_ind << 6)
- | (MODE_d << 3) | (src & 7));
+ WOUT(0x1000 | ((dst & 7) << 9) | (MODE_ind << 6) | (MODE_d << 3) | (src & 7));
}
static inline void
@@ -536,8 +534,7 @@
debug(("movew (%s), %s\n", regname(src), regname(dst)));
assert_areg(src);
assert_dreg(dst);
- WOUT = (0x3000 | ((dst & 7) << 9) | (MODE_d << 6)
- | (MODE_ind << 3) | (src & 7));
+ WOUT(0x3000 | ((dst & 7) << 9) | (MODE_d << 6) | (MODE_ind << 3) | (src & 7));
}
static inline void
@@ -546,8 +543,7 @@
debug(("movew %s, (%s)\n", regname(src), regname(dst)));
assert_dreg(src);
assert_areg(dst);
- WOUT = (0x3000 | ((dst & 7) << 9) | (MODE_ind << 6)
- | (MODE_d << 3) | (src & 7));
+ WOUT(0x3000 | ((dst & 7) << 9) | (MODE_ind << 6) | (MODE_d << 3) | (src & 7));
}
static inline void
@@ -557,9 +553,8 @@
assert_areg(src);
assert_areg(base);
assert_s16(disp);
- WOUT = (0x2000 | ((base & 7) << 9) | (MODE_inddisp << 6)
- | (MODE_a << 3) | (src & 7));
- WOUT = disp;
+ WOUT(0x2000 | ((base & 7) << 9) | (MODE_inddisp << 6) | (MODE_a << 3) | (src & 7));
+ WOUT(disp);
}
static inline void
@@ -568,8 +563,7 @@
debug(("movel %s, %s\n", regname(src), regname(dst)));
assert_areg(src);
assert_dreg(dst);
- WOUT = (0x2000 | ((dst & 7) << 9) | (MODE_d << 6)
- | (MODE_a << 3) | (src & 7));
+ WOUT(0x2000 | ((dst & 7) << 9) | (MODE_d << 6) | (MODE_a << 3) | (src & 7));
}
static inline void
@@ -578,8 +572,7 @@
debug(("movel %s, %s\n", regname(src), regname(dst)));
assert_areg(src);
assert_dreg(dst);
- WOUT = (0x2000 | ((dst & 7) << 9) | (MODE_a << 6)
- | (MODE_d << 3) | (src & 7));
+ WOUT(0x2000 | ((dst & 7) << 9) | (MODE_a << 6) | (MODE_d << 3) | (src & 7));
}
static inline void
@@ -588,8 +581,7 @@
debug(("movel %s, %s\n", regname(src), regname(dst)));
assert_dreg(src);
assert_dreg(dst);
- WOUT = (0x2000 | ((dst & 7) << 9) | (MODE_d << 6)
- | (MODE_d << 3) | (src & 7));
+ WOUT(0x2000 | ((dst & 7) << 9) | (MODE_d << 6) | (MODE_d << 3) | (src & 7));
}
static inline void
@@ -599,9 +591,8 @@
assert_dreg(src);
assert_areg(base);
assert_s16(disp);
- WOUT = (0x2000 | ((base & 7) << 9) | (MODE_inddisp << 6)
- | (MODE_d << 3) | (src & 7));
- WOUT = disp;
+ WOUT(0x2000 | ((base & 7) << 9) | (MODE_inddisp << 6) | (MODE_d << 3) | (src & 7));
+ WOUT(disp);
}
static inline void
@@ -609,8 +600,8 @@
{
debug(("movel #%d, %s\n", imm, regname(dst)));
assert_dreg(dst);
- WOUT = 0x2000 | ((dst & 7) << 9) | (MODE_d << 6) | MODE_src_imm;
- LOUT = imm;
+ WOUT(0x2000 | ((dst & 7) << 9) | (MODE_d << 6) | MODE_src_imm);
+ LOUT(imm);
}
static inline void
@@ -619,8 +610,7 @@
debug(("movel (%s), %s\n", regname(src), regname(dst)));
assert_areg(src);
assert_dreg(dst);
- WOUT = (0x2000 | ((dst & 7) << 9) | (MODE_d << 6)
- | (MODE_ind << 3) | (src & 7));
+ WOUT(0x2000 | ((dst & 7) << 9) | (MODE_d << 6) | (MODE_ind << 3) | (src & 7));
}
static inline void
@@ -629,8 +619,7 @@
debug(("movel %s, (%s)\n", regname(src), regname(dst)));
assert_areg(src);
assert_areg(dst);
- WOUT = (0x2000 | ((dst & 7) << 9) | (MODE_ind << 6)
- | (MODE_a << 3) | (src & 7));
+ WOUT(0x2000 | ((dst & 7) << 9) | (MODE_ind << 6) | (MODE_a << 3) | (src & 7));
}
static inline void
@@ -639,8 +628,7 @@
debug(("movel %s, (%s)\n", regname(src), regname(dst)));
assert_dreg(src);
assert_areg(dst);
- WOUT = (0x2000 | ((dst & 7) << 9) | (MODE_ind << 6)
- | (MODE_d << 3) | (src & 7));
+ WOUT(0x2000 | ((dst & 7) << 9) | (MODE_ind << 6) | (MODE_d << 3) | (src & 7));
}
static inline void
@@ -648,8 +636,8 @@
{
debug(("movel #%d, -(%s)\n", imm, regname(dst)));
assert_areg(dst);
- WOUT = 0x2000 | ((dst & 7) << 9) | (MODE_predec << 6) | MODE_src_imm;
- LOUT = imm;
+ WOUT(0x2000 | ((dst & 7) << 9) | (MODE_predec << 6) | MODE_src_imm);
+ LOUT(imm);
}
static inline void
@@ -658,8 +646,7 @@
debug(("movel %s, -(%s)\n", regname(src), regname(dst)));
assert_areg(src);
assert_areg(dst);
- WOUT = (0x2000 | ((dst & 7) << 9) | (MODE_predec << 6)
- | (MODE_a << 3) | (src & 7));
+ WOUT(0x2000 | ((dst & 7) << 9) | (MODE_predec << 6) | (MODE_a << 3) | (src & 7));
}
static inline void
@@ -668,8 +655,7 @@
debug(("movel +(%s), %s\n", regname(src), regname(dst)));
assert_areg(src);
assert_dreg(dst);
- WOUT = (0x2000 | ((dst & 7) << 9) | (MODE_d << 6)
- | (MODE_postinc << 3) | (src & 7));
+ WOUT(0x2000 | ((dst & 7) << 9) | (MODE_d << 6) | (MODE_postinc << 3) | (src & 7));
}
static inline void
@@ -678,8 +664,7 @@
debug(("movel +(%s), %s\n", regname(src), regname(dst)));
assert_areg(src);
assert_areg(dst);
- WOUT = (0x2000 | ((dst & 7) << 9) | (MODE_a << 6)
- | (MODE_postinc << 3) | (src & 7));
+ WOUT(0x2000 | ((dst & 7) << 9) | (MODE_a << 6) | (MODE_postinc << 3) | (src & 7));
}
static inline void
@@ -688,8 +673,7 @@
debug(("movel %s, -(%s)\n", regname(src), regname(dst)));
assert_dreg(src);
assert_areg(dst);
- WOUT = (0x2000 | ((dst & 7) << 9) | (MODE_predec << 6)
- | (MODE_d << 3) | (src & 7));
+ WOUT(0x2000 | ((dst & 7) << 9) | (MODE_predec << 6) | (MODE_d << 3) | (src & 7));
}
static inline void
@@ -699,9 +683,8 @@
assert_areg(base);
assert_s16(disp);
assert_areg(dst);
- WOUT = (0x2000 | ((dst & 7) << 9) | (MODE_predec << 6)
- | (MODE_inddisp << 3) | (base & 7));
- WOUT = disp;
+ WOUT(0x2000 | ((dst & 7) << 9) | (MODE_predec << 6) | (MODE_inddisp << 3) | (base & 7));
+ WOUT(disp);
}
static inline void
@@ -711,9 +694,8 @@
assert_areg(base);
assert_s16(disp);
assert_dreg(dst);
- WOUT = (0x2000 | ((dst & 7) << 9) | (MODE_d << 6)
- | (MODE_inddisp << 3) | (base & 7));
- WOUT = disp;
+ WOUT(0x2000 | ((dst & 7) << 9) | (MODE_d << 6) | (MODE_inddisp << 3) | (base & 7));
+ WOUT(disp);
}
static inline void
@@ -722,7 +704,7 @@
debug(("moveal %s, %s\n", regname(src), regname(dst)));
assert_areg(src);
assert_areg(dst);
- WOUT = 0x2040 | ((dst & 7) << 9) | (MODE_a << 3) | (src & 7);
+ WOUT(0x2040 | ((dst & 7) << 9) | (MODE_a << 3) | (src & 7));
}
static inline void
@@ -731,7 +713,7 @@
debug(("moveal (%s), %s\n", regname(src), regname(dst)));
assert_areg(src);
assert_areg(dst);
- WOUT = 0x2040 | ((dst & 7) << 9) | (MODE_ind << 3) | (src & 7);
+ WOUT(0x2040 | ((dst & 7) << 9) | (MODE_ind << 3) | (src & 7));
}
static inline void
@@ -741,8 +723,8 @@
assert_areg(base);
assert_s16(disp);
assert_areg(dst);
- WOUT = 0x2040 | ((dst & 7) << 9) | (MODE_inddisp << 3) | (base & 7);
- WOUT = disp;
+ WOUT(0x2040 | ((dst & 7) << 9) | (MODE_inddisp << 3) | (base & 7));
+ WOUT(disp);
}
static inline void
@@ -750,8 +732,8 @@
{
debug(("moveal #0x%x, %s\n", imm, regname(dst)));
assert_areg(dst);
- WOUT = 0x2040 | ((dst & 7) << 9) | MODE_src_imm;
- LOUT = imm;
+ WOUT(0x2040 | ((dst & 7) << 9) | MODE_src_imm);
+ LOUT(imm);
}
static inline void
@@ -760,9 +742,9 @@
debug(("moveml 0x%04x, %d(%s)\n", mask, disp, regname(areg)));
assert_s16(disp);
assert_areg(areg);
- WOUT = 0x48C0 | (MODE_inddisp << 3) | (areg & 7);
- WOUT = mask;
- WOUT = disp;
+ WOUT(0x48C0 | (MODE_inddisp << 3) | (areg & 7));
+ WOUT(mask);
+ WOUT(disp);
}
static inline void
@@ -771,9 +753,9 @@
debug(("moveml %d(%s), 0x%04x\n", disp, regname(areg), mask));
assert_s16(disp);
assert_areg(areg);
- WOUT = 0x4CC0 | (MODE_inddisp << 3) | (areg & 7);
- WOUT = mask;
- WOUT = disp;
+ WOUT(0x4CC0 | (MODE_inddisp << 3) | (areg & 7));
+ WOUT(mask);
+ WOUT(disp);
}
static inline void
@@ -781,8 +763,8 @@
{
debug(("moveml 0x%04x, -(%s)\n", mask, regname(areg)));
assert_areg(areg);
- WOUT = 0x48C0 | (MODE_predec << 3) | (areg & 7);
- WOUT = mask;
+ WOUT(0x48C0 | (MODE_predec << 3) | (areg & 7));
+ WOUT(mask);
}
static inline void
@@ -790,8 +772,8 @@
{
debug(("moveml +(%s), 0x%04x\n", regname(areg), mask));
assert_areg(areg);
- WOUT = 0x4CC0 | (MODE_postinc << 3) | (areg & 7);
- WOUT = mask;
+ WOUT(0x4CC0 | (MODE_postinc << 3) | (areg & 7));
+ WOUT(mask);
}
static inline void
@@ -800,7 +782,7 @@
debug(("moveq #%d, %s\n", imm, regname(dst)));
assert_dreg(dst);
assert_s8(imm);
- WOUT = 0x7000 | (dst << 9) | (imm & 0xFF);
+ WOUT(0x7000 | (dst << 9) | (imm & 0xFF));
}
static inline void
@@ -808,9 +790,9 @@
{
debug(("mulsl #%d, %s\n", imm, regname(dst)));
assert_dreg(dst);
- WOUT = 0x4C00 | MODE_src_imm;
- WOUT = 0x0800 | (dst << 12);
- LOUT = imm;
+ WOUT(0x4C00 | MODE_src_imm);
+ WOUT(0x0800 | (dst << 12));
+ LOUT(imm);
}
static inline void
@@ -819,8 +801,8 @@
debug(("mulsl %s, %s\n", regname(src), regname(dst)));
assert_dreg(src);
assert_dreg(dst);
- WOUT = 0x4C00 | (MODE_d << 3) | src;
- WOUT = 0x0800 | (dst << 12);
+ WOUT(0x4C00 | (MODE_d << 3) | src);
+ WOUT(0x0800 | (dst << 12));
}
static inline void
@@ -828,7 +810,7 @@
{
debug(("negl %s\n", regname(dst)));
assert_dreg(dst);
- WOUT = 0x4480 | (MODE_d << 3) | dst;
+ WOUT(0x4480 | (MODE_d << 3) | dst);
}
static inline void
@@ -836,14 +818,14 @@
{
debug(("negxl %s\n", regname(dst)));
assert_dreg(dst);
- WOUT = 0x4080 | (MODE_d << 3) | dst;
+ WOUT(0x4080 | (MODE_d << 3) | dst);
}
static inline void
op_nop(void)
{
debug(("nop\n"));
- WOUT = 0x4E71;
+ WOUT(0x4E71);
}
static inline void
@@ -852,22 +834,22 @@
debug(("orl %s, %s\n", regname(src), regname(dst)));
assert_dreg(src);
assert_dreg(dst);
- WOUT = 0x8080 | (dst << 9) | (MODE_d << 3) | src;
+ WOUT(0x8080 | (dst << 9) | (MODE_d << 3) | src);
}
static inline void
op_pea_l(int addr)
{
debug(("pea 0x%08x\n", addr));
- WOUT = 0x4840 | MODE_src_absl;
- LOUT = addr;
+ WOUT(0x4840 | MODE_src_absl);
+ LOUT(addr);
}
static inline void
op_rts(void)
{
debug(("rts\n"));
- WOUT = 0x4E75;
+ WOUT(0x4E75);
}
static inline void
@@ -875,8 +857,8 @@
{
debug(("subl #%d, %s\n", imm, regname(dst)));
assert_dreg(dst);
- WOUT = 0x9080 | (dst << 9) | MODE_src_imm;
- LOUT = imm;
+ WOUT(0x9080 | (dst << 9) | MODE_src_imm);
+ LOUT(imm);
}
static inline void
@@ -885,7 +867,7 @@
debug(("subl %s, %s\n", regname(src), regname(dst)));
assert_dreg(src);
assert_dreg(dst);
- WOUT = 0x9080 | (dst << 9) | (MODE_d << 3) | src;
+ WOUT(0x9080 | (dst << 9) | (MODE_d << 3) | src);
}
#if !defined(HAVE_NO_SUBAW)
@@ -895,8 +877,8 @@
debug(("subaw #%d, %s\n", disp, regname(dst)));
assert_s16(disp);
assert_areg(dst);
- WOUT = 0x90C0 | ((dst & 7) << 9) | MODE_src_imm;
- WOUT = disp;
+ WOUT(0x90C0 | ((dst & 7) << 9) | MODE_src_imm);
+ WOUT(disp);
}
#endif
@@ -905,8 +887,8 @@
{
debug(("subal #%d, %s\n", imm, regname(dst)));
assert_areg(dst);
- WOUT = 0x91C0 | ((dst & 7) << 9) | MODE_src_imm;
- LOUT = imm;
+ WOUT(0x91C0 | ((dst & 7) << 9) | MODE_src_imm);
+ LOUT(imm);
}
static inline void
@@ -915,7 +897,7 @@
debug(("subql #%d, %s\n", imm, regname(dst)));
assert(imm >= 1 && imm <= 8);
assert_dreg(dst);
- WOUT = 0x5180 | ((imm & 7) << 9) | (MODE_d << 3) | dst;
+ WOUT(0x5180 | ((imm & 7) << 9) | (MODE_d << 3) | dst);
}
static inline void
@@ -924,7 +906,7 @@
debug(("subxl %s, %s\n", regname(src), regname(dst)));
assert_dreg(src);
assert_dreg(dst);
- WOUT = 0x9180 | (dst << 9) | src;
+ WOUT(0x9180 | (dst << 9) | src);
}
static inline void
@@ -932,7 +914,7 @@
{
debug(("tst %s\n", regname(src)));
assert_areg(src);
- WOUT = 0x4A80 | (MODE_a << 3) | (src & 7);
+ WOUT(0x4A80 | (MODE_a << 3) | (src & 7));
}
static inline void
@@ -940,7 +922,7 @@
{
debug(("tst %s\n", regname(src)));
assert_dreg(src);
- WOUT = 0x4A80 | (MODE_d << 3) | (src & 7);
+ WOUT(0x4A80 | (MODE_d << 3) | (src & 7));
}
static inline void
@@ -948,7 +930,7 @@
{
debug(("unlk %s\n", regname(areg)));
assert_areg(areg);
- WOUT = 0x4E58 | (areg & 7);
+ WOUT(0x4E58 | (areg & 7));
}
/* --------------------------------------------------------------------- */
@@ -958,8 +940,8 @@
{
assert_freg(src);
assert_freg(dst);
- WOUT = 0xF000 | (COPROCID << 9);
- WOUT = ((src & 7) << 10) | ((dst & 7) << 7) | opmode;
+ WOUT(0xF000 | (COPROCID << 9));
+ WOUT(((src & 7) << 10) | ((dst & 7) << 7) | opmode);
}
static inline void
@@ -996,8 +978,8 @@
debug(("fmoves %s, (%s)\n", regname(src), regname(base)));
assert_freg(src);
assert_areg(base);
- WOUT = 0xF000 | (COPROCID << 9) | (MODE_ind << 3) | (base & 7);
- WOUT = 0x6400 | ((src & 7) << 7);
+ WOUT(0xF000 | (COPROCID << 9) | (MODE_ind << 3) | (base & 7));
+ WOUT(0x6400 | ((src & 7) << 7));
}
static inline void
@@ -1006,8 +988,8 @@
*** Patch too long, truncated ***
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