[kaffe] CVS kaffe (guilhem): Support for old GCC compiler in mips/atomic.
Kaffe CVS
cvs-commits at kaffe.org
Tue Jun 21 12:44:39 PDT 2005
PatchSet 6657
Date: 2005/06/21 19:36:30
Author: guilhem
Branch: HEAD
Tag: (none)
Log:
Support for old GCC compiler in mips/atomic.
Members:
ChangeLog:1.4183->1.4184
config/mips/atomic.h:1.4->1.5
Index: kaffe/ChangeLog
diff -u kaffe/ChangeLog:1.4183 kaffe/ChangeLog:1.4184
--- kaffe/ChangeLog:1.4183 Tue Jun 21 16:41:31 2005
+++ kaffe/ChangeLog Tue Jun 21 19:36:30 2005
@@ -1,9 +1,16 @@
2005-06-21 Guilhem Lavaux <guilhem at kaffe.org>
+ * config/mips/atomic.h: Removed all register aliases to support
+ old gcc compiler.
+
+ Reported by Riccardo Mottola <rmottola at users.sf.net>
+
+2005-06-21 Guilhem Lavaux <guilhem at kaffe.org>
+
* config/config-hacks.c: We must redefine __builtin_trap until gcc
3.1.
- Reported by Andrew Pinsky <pinskia at physics.uc.edu>
+ Reported by Andrew Pinski <pinskia at physics.uc.edu>
2005-06-21 Guilhem Lavaux <guilhem at kaffe.org>
Index: kaffe/config/mips/atomic.h
diff -u kaffe/config/mips/atomic.h:1.4 kaffe/config/mips/atomic.h:1.5
--- kaffe/config/mips/atomic.h:1.4 Tue Jun 21 15:17:16 2005
+++ kaffe/config/mips/atomic.h Tue Jun 21 19:36:36 2005
@@ -167,21 +167,19 @@
({ \
unsigned int __ret, __tmp; \
__asm__ __volatile__ ( \
- " .set push\n" \
- " .set mips2\n" \
" .set noreorder\n" \
mb1 \
- "1: ll %[__ret],%[__mem]\n" \
- " move %[__tmp],%[__val]\n" \
- " sc %[__tmp],%[__mem]\n" \
- " beqz %[__tmp],1b\n" \
+ "1: ll %0,%2\n" \
+ " move %1,%3\n" \
+ " sc %1,%2\n" \
+ " beqz %1,1b\n" \
" nop\n" \
mb2 \
- " .set pop\n" \
- : [__ret] "=&r" (__ret), \
- [__tmp] "=&r" (__tmp) \
- : [__mem] "R" (*mem), \
- [__val] "r" ((unsigned int)(value)) \
+ " .set reorder\n" \
+ : "=&r" (__ret), \
+ "=&r" (__tmp) \
+ : "R" (*mem), \
+ "r" ((unsigned int)(value)) \
: "memory"); \
__ret; })
@@ -193,21 +191,19 @@
({ \
unsigned long __ret, __tmp; \
__asm__ __volatile__ ( \
- " .set push\n" \
- " .set mips3\n" \
" .set noreorder\n" \
mb1 \
- "1: lld %[__ret],%[__mem]\n" \
- " move %[__tmp],%[__val]\n" \
- " scd %[__tmp],%[__mem]\n" \
- " beqz %[__tmp],1b\n" \
+ "1: lld %0,%2\n" \
+ " move %1,%3\n" \
+ " scd %1,%2\n" \
+ " beqz %1,1b\n" \
" nop\n" \
mb2 \
- " .set pop\n" \
- : [__ret] "=&r" (__ret), \
- [__tmp] "=&r" (__tmp) \
- : [__mem] "R" (*mem), \
- [__val] "r" (value) \
+ " .set reorder\n" \
+ : "=&r" (__ret), \
+ "=&r" (__tmp) \
+ : "R" (*mem), \
+ "r" (value) \
: "memory"); \
__ret; })
#endif
@@ -231,21 +227,19 @@
({ \
unsigned int __ret, __tmp; \
__asm__ __volatile__ ( \
- " .set push\n" \
- " .set mips2\n" \
" .set noreorder\n" \
mb1 \
- "1: ll %[__ret],%[__mem]\n" \
- " addu %[__tmp],%[__val],%[__ret]\n" \
- " sc %[__tmp],%[__mem]\n" \
- " beqz %[__tmp],1b\n" \
+ "1: ll %0,%2\n" \
+ " addu %1,%4,%0\n" \
+ " sc %1,%2\n" \
+ " beqz %1,1b\n" \
" nop\n" \
mb2 \
- " .set pop\n" \
- : [__ret] "=&r" (__ret), \
- [__tmp] "=&r" (__tmp) \
- : [__mem] "R" (*mem), \
- [__val] "r" ((unsigned int)(value)) \
+ " .set reorder\n" \
+ : "=&r" (__ret), \
+ "=&r" (__tmp) \
+ : "R" (*mem), \
+ "r" ((unsigned int)(value)) \
: "memory"); \
__ret; })
@@ -257,21 +251,19 @@
({ \
unsigned long __ret, __tmp; \
__asm__ __volatile__ ( \
- " .set push\n" \
- " .set mips3\n" \
" .set noreorder\n" \
mb1 \
- "1: lld %[__ret],%[__mem]\n" \
- " daddu %[__tmp],%[__val],%[__ret]\n" \
- " scd %[__tmp],%[__mem]\n" \
- " beqz %[__tmp],1b\n" \
+ "1: lld %0,%2\n" \
+ " daddu %1,%3,%0\n" \
+ " scd %1,%2\n" \
+ " beqz %1,1b\n" \
" nop\n" \
mb2 \
- " .set pop\n" \
- : [__ret] "=&r" (__ret), \
- [__tmp] "=&r" (__tmp) \
- : [__mem] "R" (*mem), \
- [__val] "r" ((unsigned long)(value)) \
+ " .set reorder\n" \
+ : "=&r" (__ret), \
+ "=&r" (__tmp) \
+ : "R" (*mem), \
+ "r" ((unsigned long)(value)) \
: "memory"); \
__ret; })
#endif
@@ -294,20 +286,18 @@
({ \
unsigned int __ret, __tmp; \
__asm__ __volatile__ ( \
- " .set push\n" \
- " .set mips2\n" \
" .set noreorder\n" \
mb1 \
- "1: ll %[__ret],%[__mem]\n" \
- " addiu %[__tmp],%[__ret],1\n" \
- " sc %[__tmp],%[__mem]\n" \
- " beqz %[__tmp],1b\n" \
- " addiu %[__ret],%[__ret],1\n" \
- mb2 \
- " .set pop\n" \
- : [__ret] "=&r" (__ret), \
- [__tmp] "=&r" (__tmp) \
- : [__mem] "R" (*mem) \
+ "1: ll %0,%2\n" \
+ " addiu %0,%1,1\n" \
+ " sc %0,%2\n" \
+ " beqz %0,1b\n" \
+ " addiu %0,%0,1\n" \
+ mb2 \
+ " .set reorder\n" \
+ : "=&r" (__ret), \
+ "=&r" (__tmp) \
+ : "R" (*mem) \
: "memory"); \
__ret; })
@@ -319,20 +309,18 @@
({ \
unsigned long __ret, __tmp; \
__asm__ __volatile__ ( \
- " .set push\n" \
- " .set mips3\n" \
" .set noreorder\n" \
mb1 \
- "1: lld %[__ret],%[__mem]\n" \
- " daddiu %[__tmp],%[__ret],1\n" \
- " scd %[__tmp],%[__mem]\n" \
- " beqz %[__tmp],1b\n" \
- " daddiu %[__ret],%[__ret],1\n" \
- mb2 \
- " .set pop\n" \
- : [__ret] "=&r" (__ret), \
- [__tmp] "=&r" (__tmp) \
- : [__mem] "R" (*mem) \
+ "1: lld %0,%2\n" \
+ " daddiu %1,%0,1\n" \
+ " scd %1,%2\n" \
+ " beqz %1,1b\n" \
+ " daddiu %0,%0,1\n" \
+ mb2 \
+ " .set reorder\n" \
+ : "=&r" (__ret), \
+ "=&r" (__tmp) \
+ : "R" (*mem) \
: "memory"); \
__ret; })
#endif
@@ -358,20 +346,18 @@
({ \
unsigned int __ret, __tmp; \
__asm__ __volatile__ ( \
- " .set push\n" \
- " .set mips2\n" \
" .set noreorder\n" \
mb1 \
- "1: ll %[__ret],%[__mem]\n" \
- " addiu %[__tmp],%[__ret],-1\n" \
- " sc %[__tmp],%[__mem]\n" \
- " beqz %[__tmp],1b\n" \
- " addiu %[__ret],%[__ret],-1\n" \
- mb2 \
- " .set pop\n" \
- : [__ret] "=&r" (__ret), \
- [__tmp] "=&r" (__tmp) \
- : [__mem] "R" (*mem) \
+ "1: ll %0,%2\n" \
+ " addiu %1,%0,-1\n" \
+ " sc %1,%2\n" \
+ " beqz %1,1b\n" \
+ " addiu %0,%0,-1\n" \
+ mb2 \
+ " .set reorder\n" \
+ : "=&r" (__ret), \
+ "=&r" (__tmp) \
+ : "R" (*mem) \
: "memory"); \
__ret; })
@@ -383,20 +369,18 @@
({ \
unsigned long __ret, __tmp; \
__asm__ __volatile__ ( \
- " .set push\n" \
- " .set mips3\n" \
" .set noreorder\n" \
mb1 \
- "1: lld %[__ret],%[__mem]\n" \
- " daddiu %[__tmp],%[__ret],-1\n" \
- " scd %[__tmp],%[__mem]\n" \
- " beqz %[__tmp],1b\n" \
- " daddiu %[__ret],%[__ret],-1\n" \
- mb2 \
- " .set pop\n" \
- : [__ret] "=&r" (__ret), \
- [__tmp] "=&r" (__tmp) \
- : [__mem] "R" (*mem) \
+ "1: lld %0,%2\n" \
+ " daddiu %1,%0,-1\n" \
+ " scd %1,%2\n" \
+ " beqz %1,1b\n" \
+ " daddiu %0,%0,-1\n" \
+ mb2 \
+ " .set reorder\n" \
+ : "=&r" (__ret), \
+ "=&r" (__tmp) \
+ : "R" (*mem) \
: "memory"); \
__ret; })
#endif
@@ -422,23 +406,21 @@
({ \
signed int __ret, __tmp; \
__asm__ __volatile__ ( \
- " .set push\n" \
- " .set mips2\n" \
" .set noreorder\n" \
mb1 \
- "1: ll %[__ret],%[__mem]\n" \
- " addiu %[__tmp],%[__ret],-1\n" \
- " bltz %[__tmp],2f\n" \
+ "1: ll %0,%2\n" \
+ " addiu %1,%0,-1\n" \
+ " bltz %1,2f\n" \
" nop\n" \
- " sc %[__tmp],%[__mem]\n" \
- " beqz %[__tmp],1b\n" \
+ " sc %1,%2\n" \
+ " beqz %1,1b\n" \
" nop\n" \
mb2 \
"2:\n" \
- " .set pop\n" \
- : [__ret] "=&r" (__ret), \
- [__tmp] "=&r" (__tmp) \
- : [__mem] "R" (*mem) \
+ " .set reorder\n" \
+ : "=&r" (__ret), \
+ "=&r" (__tmp) \
+ : "R" (*mem) \
: "memory"); \
__ret; })
@@ -450,23 +432,21 @@
({ \
signed long __ret, __tmp; \
__asm__ __volatile__ ( \
- " .set push\n" \
- " .set mips3\n" \
" .set noreorder\n" \
mb1 \
- "1: lld %[__ret],%[__mem]\n" \
- " daddiu %[__tmp],%[__ret],-1\n" \
- " bltz %[__tmp],2f\n" \
+ "1: lld %0,%2\n" \
+ " daddiu %1,%0,-1\n" \
+ " bltz %1,2f\n" \
" nop\n" \
- " scd %[__tmp],%[__mem]\n" \
- " beqz %[__tmp],1b\n" \
+ " scd %1,%2\n" \
+ " beqz %1,1b\n" \
" nop\n" \
mb2 \
"2:\n" \
- " .set pop\n" \
- : [__ret] "=&r" (__ret), \
- [__tmp] "=&r" (__tmp) \
- : [__mem] "R" (*mem) \
+ " .set reorder\n" \
+ : "=&r" (__ret), \
+ "=&r" (__tmp) \
+ : "R" (*mem) \
: "memory"); \
__ret; })
#endif
@@ -487,22 +467,20 @@
({ \
unsigned int __ret, __tmp; \
__asm__ __volatile__ ( \
- " .set push\n" \
- " .set mips2\n" \
" .set noreorder\n" \
mb1 \
- "1: ll %[__tmp],%[__mem]\n" \
- " or %[__ret],%[__tmp],%[__bit]\n" \
- " sc %[__ret],%[__mem]\n" \
- " beqz %[__ret],1b\n" \
- " and %[__ret],%[__tmp],%[__bit]\n" \
+ "1: ll %1,%2\n" \
+ " or %0,%1,%3\n" \
+ " sc %0,%2\n" \
+ " beqz %0,1b\n" \
+ " and %0,%2,%3\n" \
mb2 \
"2:\n" \
- " .set pop\n" \
- : [__ret] "=&r" (__ret), \
- [__tmp] "=&r" (__tmp) \
- : [__mem] "R" (*mem), \
- [__bit] "r" (1UL << bit) \
+ " .set reorder\n" \
+ : "=&r" (__ret), \
+ "=&r" (__tmp) \
+ : "R" (*mem), \
+ "r" (1UL << bit) \
: "memory"); \
__ret != 0; })
@@ -514,22 +492,20 @@
({ \
unsigned long __ret, __tmp; \
__asm__ __volatile__ ( \
- " .set push\n" \
- " .set mips3\n" \
" .set noreorder\n" \
mb1 \
- "1: lld %[__tmp],%[__mem]\n" \
- " or %[__ret],%[__tmp],%[__bit]\n" \
- " scd %[__ret],%[__mem]\n" \
- " beqz %[__ret],1b\n" \
- " and %[__ret],%[__tmp],%[__bit]\n" \
+ "1: lld %1,%2\n" \
+ " or %0,%1,%3\n" \
+ " scd %0,%2\n" \
+ " beqz %0,1b\n" \
+ " and %0,%1,%2\n" \
mb2 \
"2:\n" \
- " .set pop\n" \
- : [__ret] "=&r" (__ret), \
- [__tmp] "=&r" (__tmp) \
- : [__mem] "R" (*mem), \
- [__bit] "r" (1 << bit) \
+ " .set reorder\n" \
+ : "=&r" (__ret), \
+ "=&r" (__tmp) \
+ : "R" (*mem), \
+ "r" (1 << bit) \
: "memory"); \
__ret; })
#endif
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