MIPS deadlock bug fix

[Slegers, Walter]

Hi Edouard,

> Could you review my COMPARE_AND_EXCHANGE for MIPS II before I commit it,
> I'm learning MIPS assembly :-)

I know the idea behind the ll and sc instructions but I don't have any
practical
experience with them as they are not available on my R3000. When I look at
your code then I think you have correctly applied the principle behind the
ll and
sc instruction. You however seem to have missed a branch delay slot.

> /*
>  * Do an atomic compare and exchange.  The address 'A' is checked against

>  * value 'O' and if they match it's exchanged with value 'N'.
>  * We return '1' if the exchange is sucessful, otherwise 0.
>  */
> /* Note that this version use MIPS II ll/sc instructions */
> #define COMPARE_AND_EXCHANGE(A,O,N)		\
> ({						\
> 	unsigned int tmp, ret;			\
>  						\
> 	asm volatile(				\
> 	"	.set	noreorder\n"		\
> 	"	.set	mips2\n"		\
> 	"	li	%1, 0\n"		\
> 	"1:	ll	%0, %3\n"		\
> 	"	bne	%0, %4, 2f\n"		\

This is a branch delay slot.
But the instruction below doesn't harm you.
So all is fine here.

> 	"	move	%0, %5\n"		\
> 	"	sc	%0, %2\n"		\
> 	"	beqz	%0, 1b\n"		\

This is another branch delay slot.
The instruction below is always executed, even if you branch back to 1.
Meaning that ret will be set to 1 even if you jump back. This is not what
you want, add a nop here.

> 	"	li	%1, 1\n"		\
> 	"2:	.set	mips0\n"		\
> 	"	.set	reorder\n"		\
> 	: "=&r" (tmp), "=r" (ret), "=m" (*(A))	\
> 	: "m" (*(A)), "r" (O), "r" (N)		\
> 	: "memory");				\
> 	ret;					\
> })

Kind regards,
    Walter Slegers



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